This invention relates generally to mobile computing systems, and more specifically to a method for reducing power consumption of the same.
The emphasis in mobile computing system (MCS) design is to reduce size and weight while increasing operating frequencies. One way in which MCSs have been reduced in size and weight is through a reduction in battery size. Today, MCSs may operate at frequencies of 850 MHz or more and these higher frequencies require more power. Therefore the emphasis on size reduction and increased performance has led to an emphasis on power conservation.
Most personal computers including MCSs use dynamic random access memory (DRAM) as main memory due to the DRAM""s low cost per bit and low power consumption. A typical DRAM storage cell is shown in FIG. 1. The basic memory storage cell 100, shown in FIG. 1, is a capacitor, that is, an integrated capacitor 105 connected in series with a control transistor 110. The control transistor 110 acts as an on-off switch. To store data in, or read data from, the memory cell, the control transistor 110 is turned on, by applying a positive pulse to control line (word line) 115. When the control transistor 110 is turned off, the integrated capacitor 105 is isolated from the rest of the circuitry. The state of memory storage cell 100 is retained in the charge on integrated capacitor 105. When the integrated capacitor 105 is charged, a binary 1 is stored. When the integrated capacitor 105 is discharged, a binary 0 is stored. To read data from memory storage cell 100 the control transistor 110 is turned on connecting the integrated capacitor 105 to sense line (bit line) 120. External circuitry examines the state of integrated capacitor 105 and informs the central processing unit (CPU).
The capacitance in a memory storage cell is very small and therefore, any charge on it will quickly leak off. This would alter the state of the memory storage cell and the stored data would be lost. To avoid lost data, the charge on the cell is periodically refreshed. Typically the memory storage cell is refreshed approximately every two milliseconds. This refreshing process consumes power that, as a percentage of total power consumption, becomes significant in a MCS during some modes of operation.